Systems and Methods for Adding a Delay to a Signal

ABSTRACT

Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination is made in response to determining the path length to the device.

I. CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. provisional application Ser. No. 60/883,018, filed on Dec. 31, 2006, the entire contents of which are incorporated by reference herein.

II. BACKGROUND

The invention relates generally to generating, delaying, and transmitting signals.

In many applications, signals that are generated at a first location and transmitted to a second location need to arrive at the second location having a desired phase. It may be difficult, however, to control the phase in cases where the signal path length from the first to the second location is not well known.

This may be the case, for example, when clock generators generate clock signals that are to be sent to multiple devices over different signal paths on a board. Though it may be desirable for the clock signals to arrive at the devices having the same phase, differences in delays that may be added by the different signal paths, for example, may lead to the clock signals arriving at the different devices having different phases.

Systems and methods are therefore required that can control the phase of signals travelling over signals paths that can introduce unknown delays to the signals.

III. SUMMARY

In one respect, disclosed is a method for transmitting a signal, the method comprising: determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line in response to the determining the path length to the device, the signal having a desired phase at the device.

In another respect, disclosed is a delay device comprising: a delay controller; and a delay generator coupled to the delay controller, the delay generator being coupled to a transmission line, the transmission line coupling a signal generator and a device; the delay controller being configured to determine a signal path length from the signal generator to the device; and the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.

In yet another respect, disclosed is a computer program product stored on a computer operable medium, the computer program product comprising software code being effective to: determine a signal path length to a device over a transmission line; and add a delay to a signal to be transmitted over a transmission line in response to the system determining the signal path length to the device, the signal having a desired phase at the device.

In yet another respect, disclosed is an information handling system comprising: one or more processors; a memory unit coupled to the one or more processors; a communications device coupled to the one or more processors; and a delay device coupled to the one or more processors, the delay device comprising: a delay controller; and a delay generator coupled to the delay controller, the delay generator being coupled to a transmission line, the transmission line coupling a signal generator and a device; the delay controller being configured to determine a signal path length from the signal generator to the device; and the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.

Numerous additional embodiments are also possible.

IV. BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention may become apparent upon reading the detailed description and upon reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a system for determining and appropriately adjusting the delay of a signal, in accordance with some embodiments.

FIG. 2 is a block diagram illustrating a system for determining and appropriately adjusting the delay of clock signals for a group of electronic devices, in accordance with some embodiments.

FIG. 3 is a flow diagram illustrating a method for determining and appropriately adjusting the delay of a signal, in accordance with some embodiments.

FIG. 4 is a flow diagram illustrating a method for determining and appropriately adjusting the delay of clock signals for a group of devices, in accordance with some embodiments.

FIG. 5 is a block diagram illustrating an information handling system that includes a delay device, in accordance with some embodiments.

While the invention is subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and the accompanying detailed description. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular embodiments. This disclosure is instead intended to cover all modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims.

V. DETAILED DESCRIPTION

One or more embodiments of the invention are described below. It should be noted that these and any other embodiments are exemplary and are intended to be illustrative of the invention rather than limiting. While the invention is widely applicable to different types of systems, it is impossible to include all of the possible embodiments and contexts of the invention in this disclosure. Upon reading this disclosure, many alternative embodiments of the present invention will be apparent to persons of ordinary skill in the art.

FIG. 1 is a block diagram illustrating a system for determining and appropriately adjusting the delay of a signal, in accordance with some embodiments. In some embodiments, delay device 130 includes delay controller 120 and delay generator 125, which is coupled to delay generator 125. In other embodiments, delay controller 120 and delay generator 125 may be included in the same device. Other configurations are also possible. Delay generator 125 is coupled to signal generator 110 and to device 115 using signal path 130.

In some embodiments, signal generator 110 is configured to generate a signal intended for device 115. The signal may travel to device 115 over signal path 130, which can add a delay to the signal. In the case of an electrical signal, for example, the delay may be due to the length of the signal path, the speed at which the signal travels, other devices connected along the signal path, impedances along the signal path, and so on. The delay introduced to the signal may also depend on the frequency of the signal, the ambient or board temperature, and so on.

In some embodiments, it may be desirable for the signal to arrive at device 115 having a desired phase. Due to the various delays that may be introduced into the signal path, the phase of the signal at device 115 may be unpredictable. Delay controller 120 is configured to determine a signal path length of signal path 130. In some embodiments, delay controller 120 may determine the signal path length of signal path 130 by transmitting a measurement signal over signal path 130 through delay generator 125 and by determining the time it takes for a reflected signal to return. In some embodiments, delay controller may be programmed with a predicted time and amplitude value so that delay controller 120 can reject false reflected signals that are not caused by device 115. That is, delay controller 120 may only keep measured time values and amplitudes that are within a certain range of the predicted time and amplitude value. The length may be computed, for example, by multiplying the velocity of the signal with half the time it takes for the measurement signal to return.

After determining the signal length of signal path 130 and by being provided (or by being programmed with) a desired phase at device 115, delay controller 120 determines a delay value to be added to signal path 130 to accomplish the desired phase. Delay controller 120 may then provide (or program) delay generator 125 with the appropriate delay. Delay generator 125 is configured to implement the delay on signal path 130. In the case of electrical signals, for example, delay generator 125 may use delay-locked loop circuitry to generate the appropriate delay.

In some embodiments, delay controller 120 may recompute an appropriate delay value either periodically or on demand in order to ensure that the signal from signal generator 125 continues to arrive at device 115 with the appropriate phase. In some embodiments, device 115 may be a processor, a memory, or any other device that may require a signal for timing the operation of the device, for example.

FIG. 2 is a block diagram illustrating a system for determining and appropriately adjusting the delay of clock signals for a group of electronic devices, in accordance with some embodiments. In some embodiments, clock signal generator 210 is configured to generate a clock signal, which is to be used to synchronize one or more of devices 215, 220, 225, and 230. In one example embodiment, in terms of timing, device 215 may be required to be in phase with device 220 and device 225 may be required to be in phase with device 230, while the first pair of devices may be required to be 180 degrees out of phase with the second pair of devices. In some embodiments, clock signal generator 210 may be implemented using a phase-locked loop (PLL) coupled to a voltage-controlled crystal oscillator (VCXO).

Due to variations in the electrical lengths of transmission lines 235, 240, 245, and 250, the clock signal may arrive at each the devices with different and unpredicted phase. Delay controller 295 is configured to determine appropriate delay values to be added to each of the paths in order for the clock signals arriving at the devices to have an appropriate phase depending on the application. For example, if the clock signals are intended to synchronize two or more devices, appropriate delays are added to ensure that the clock signals arrive at the devices at the same time regardless of the different signal paths for the clock signals.

Delay controller 295 is configured to determine the electrical path lengths of transmission lines 235, 240, 245, and 250. In some embodiments, delay controller 295 may determine the electrical path lengths by transmitting measurement signals down each of the transmission lines and by determining the time it takes for the reflected signals to return. In some embodiments, delay controller 295 may be programmed with predicted time values corresponding to each device, thereby enabling the delay controller to reject false reflected signals that are not caused by the devices.

After determining the signal path lengths of the transmission lines and by being provided (or by being programmed with) a desired phase for each device, delay controller 295 determines delay values to be added to the transmission lines to accomplish the desired phase. Delay controller 295 may then provide (or program) delay generators 255, 260, 265, and 270 with the appropriate delay. The delay generators are then configured to introduce the appropriate delays to the transmission lines. In some embodiments, the delay generators may be implemented using delay locked loop circuitry.

In some embodiments, the delay controller may recompute appropriate delay values either periodically or on demand in order to ensure that the clock signals from the signal generator continue to arrive at the devices with the appropriate phase values.

FIG. 3 is a flow diagram illustrating a method for determining and appropriately adjusting the delay of a signal, in accordance with some embodiments. Processing begins at 300 whereupon, at block 315, a signal path length of a signal path to a device is determined. The signal path may be an electrical transmission line for transmitting electrical signals or it may be another type of transmission line (including a wireless one) for transmitting other types of signals. In some embodiments, the signal path length may be determined by transmitting a measurement signal down the signal path and by computing the time it takes for a reflected signal to return. In some embodiments, the time value obtained may be compared to a predicted time and amplitude value so that false reflected signals can be rejected. In some embodiments, the signal path length may be determined by a device such as delay controller 120.

At block 320, a signal to be transmitted over the signal path to the device is generated. In some embodiments, the signal path can add an unpredicted amount of delay to the signal, thereby causing the signal to arrive at the device with an unpredicted phase. In some embodiments, the signal may be generated by a device such as signal generator 110.

At block 325, a delay is added to the signal. In some embodiments, the delay is added in response to determining the signal path length and knowledge (either stored or inputted) of the desired phase for the signal at the device. A delay may be added to the signal, for example, to ensure that the signal arrives at the device having a desired phase. The delay may be included, in some embodiments, to compensate for delays that may be introduced into the signal path. In the case of an electrical signal, for example, the delay may be due to the length of the signal path, the speed at which the signal travels, other devices connected along the signal path, impedances, and so on. The delay introduced into the signal may also depend on the frequency of the signal, the ambient or board temperature, and so on. Processing subsequently ends at 399. In some embodiments, a delay may be added by a device such as delay generator 125.

In some embodiments, an appropriate delay value may be recomputed either periodically or on demand in order to ensure that the signal from the signal generator continues to arrive at the device having the appropriate phase.

FIG. 4 is a flow diagram illustrating a method for determining and appropriately adjusting the delay of clock signals for a group of devices, in accordance with some embodiments. Processing begins at 400, whereupon, at block 410, the electrical lengths of transmission lines coupling a clock generator (for generating a clock signal) to groups of multiple devices are determined. In some embodiments, due to variations in the electrical lengths of the transmission lines, the clock signal from the clock generator may arrive at the devices having unpredicted phase values. Thus it may be necessary to measure the electrical length of and introduce delays into the transmission lines to control the phase with which the clock signal will arrive at the devices. In some embodiments, clock signals may be generated by a device such as clock signal generator 210 and the delay may be generated by devices such as delay generators 255, 260, 265, and 270.

In some embodiments, the electrical lengths may be determined by transmitting measurement signals down each of the transmission lines and by determining the time it takes for the reflected signals to return. The length, for example, may be calculated by multiplying the velocity with which the signals travel by the determined time. In some embodiments, the measured time may be compared to a predicted time and amplitude values so that false reflected signals may be rejected.

At block 415, a clock signal is generated. The clock signal, in some embodiments, may be sent to the multiple devices over the transmission lines in order to synchronize the devices within one or more groups. For example, devices in a first group may be in phase with each other, devices in a second group may be in phase with each other, and the devices in the first group may be 180 degrees out of phase with the devices in the second group.

At block 420, a delay to be added to each transmission line is determined. The delays are such that the devices receive clock signals having a desired phase. In some embodiments, the delay values are determined using a provided (or preprogrammed) desired phase for each device and the electrical signal length for each transmission line. At block 425, the computed delays are added to the corresponding transmission lines in order to obtain the desired clock signal phase at each device.

At block 430, the delay values may be recomputed as necessary (either periodically or on demand) to ensure that the signals from the signal generator continue to arrive at the devices having appropriate phase values. Processing subsequently ends at 499.

FIG. 5 is a block diagram illustrating an information handling system that includes a delay device, in accordance with some embodiments. In some embodiments, information handling system 510 may include a processor/controller 515 for processing data. Processor/controller 515 may be coupled to memory 520 for storing information and to communications device 525 for communicating with other devices. Information handling system 510 may also include delay device 530, which, in some embodiments, has functionality similar to the functionality of delay device 130. Delay device 530 is configured to control the delays for signals being used in information handling system 510, such as signals generated by signal generator 110 and intended for device 115.

Those of skill will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The benefits and advantages that may be provided by the present invention have been described above with regard to specific embodiments. These benefits and advantages, and any elements or limitations that may cause them to occur or to become more pronounced are not to be construed as critical, required, or essential features of any or all of the claims. As used herein, the terms “comprises,” “comprising,” or any other variations thereof, are intended to be interpreted as non-exclusively including the elements or limitations which follow those terms. Accordingly, a system, method, or other embodiment that comprises a set of elements is not limited to only those elements, and may include other elements not expressly listed or inherent to the claimed embodiment.

While the present invention has been described with reference to particular embodiments, it should be understood that the embodiments are illustrative and that the scope of the invention is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described above are possible. It is contemplated that these variations, modifications, additions and improvements fall within the scope of the invention as detailed within the following claims. 

1. A method for transmitting a signal, the method comprising: determining a signal path length to a device over a transmission line; and adding a delay to a signal to be transmitted over the transmission line in response to the determining the signal path length to the device, the signal having a desired phase at the device.
 2. The method of claim 1, where the signal is an electrical clock signal.
 3. The method of claim 2, where the electrical clock signal is generated using a phase-locked loop and a voltage-controlled crystal oscillator.
 4. The method of claim 1, further comprising: determining additional signal path lengths to additional devices over additional transmission lines; and adding delays to additional signals to be transmitted over the additional transmission lines in response to the determining the additional signal path lengths to the additional devices, the additional signals having desired phases at each of the devices.
 5. The method of claim 4, further comprising adjusting the delay and the additional delays such that the signal and the additional signals have equal phase at each of the devices.
 6. The method of claim 1, where the determining the signal path length comprises: sending a signal pulse on the transmission line; receiving a reflection of the signal from the device; and computing the signal path length by determining a roundtrip time and amplitude for the signal.
 7. The method of claim 6, further comprising: receiving false reflections of the signal; and detecting and ignoring the false reflections of the signal using an estimated roundtrip time and an estimated amplitude for the signal.
 8. The method of claim 1, where the adding the delay comprises adding the delay using a delay-locked loop.
 9. An apparatus comprising: a delay controller; and a delay generator coupled to the delay controller, the delay generator being configured to couple to a transmission line, the transmission line coupling a signal generator and a device; the delay controller being configured to determine a signal path length from the signal generator to the device; and the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.
 10. The apparatus of claim 9, where the signal is an electrical clock signal.
 11. The apparatus of claim 10, where the signal generator comprises a phase-locked loop coupled to a voltage-controlled crystal oscillator for generating the electrical clock signal.
 12. The apparatus of claim 9, where: the delay controller is further configured to determine additional signal path lengths of additional transmission lines, the additional transmission lines coupling the signal generator to additional devices; and additional delay generators coupled to the additional transmission lines are configured to add additional delays to additional signals to be transmitted over the additional transmission lines in response to the delay controller determining the additional signal path lengths to the additional devices, the signals having additional desired phases at each of the additional devices.
 13. The apparatus of claim 12, where the delay controller is further configured to adjust the delay and the additional delays such that the signal and the additional signals have equal phases at each of the devices.
 14. The apparatus of claim 9, where the delay controller being configured to determine the signal path length comprises the system being configured to: send a signal pulse on the transmission line; receive a reflection of the signal from the device; and compute the signal path length by determining a roundtrip time and amplitude for the signal.
 15. The apparatus of claim 14, the delay controller is further configured to: receive false reflections of the signal; and detect and ignore the false reflections of the signal using an estimated roundtrip time and amplitude for the signal.
 16. The apparatus of claim 9, where the delay generator comprises a delay-locked loop.
 17. A computer program product stored on a computer operable medium, the computer program product comprising software code being effective to: determine a signal path length to a device over a transmission line; and cause a delay to be added to a signal to be transmitted over a transmission line in response to the code being effective to determine the signal path length to the device, the signal having a desired phase at the device.
 18. The product of claim 17, where the signal is an electrical clock signal.
 19. The product of claim 18, where the electrical clock signal is generated using a phase-locked loop and a voltage-controlled crystal oscillator.
 20. The product of claim 17, where the code is further configured to: determine additional signal path lengths to additional devices over additional transmission lines; and add additional delays to additional signals to be transmitted over the additional transmission lines in response to the code being effective to determine the additional signal path lengths to the additional devices, the additional signals having additional desired phases at each of the additional devices.
 21. The product of claim 20, where the code is further effective to adjust the delay and the additional delays such that the signal and the additional signals have equal phases at each of the device and the additional devices.
 22. The product of claim 17, where the code being effective to determine the signal path length comprises the code being effective to: cause a signal pulse to be sent on the transmission line; cause a reflection of the signal from the device to be detected; and compute the signal path length by determining a roundtrip time and amplitude for the signal.
 23. The product of claim 22, the code is further effective to: cause a detection of additional false reflections of the signal; and cause the false reflections of the signal to be detected and ignored using an estimated roundtrip time and amplitude for the signal.
 24. The product of claim 17, where the code being effective to add the delay comprises the code being configured to cause the delay to be added using a delay-locked loop.
 25. An information handling system comprising: one or more processors; a memory unit coupled to the one or more processors; a communications device coupled to the one or more processors; and a delay device coupled to the one or more processors, the delay device comprising: a delay controller; and a delay generator coupled to the delay controller, the delay generator being configured to couple to a transmission line, the transmission line coupling a signal generator and a device; the delay controller being configured to determine a signal path length from the signal generator to the device; and the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.
 26. The information handling system of claim 25, where the signal is an electrical clock signal.
 27. The information handling system of claim 26, where the signal generator comprises a phase-locked loop coupled to a voltage-controlled crystal oscillator for generating the electrical clock signal. 